1. Field of the Invention
The present invention relates generally to electronic crosspoint switching devices in communication, and particularly to improvements of signal transmission rates on electronic crosspoint switching devices. The present invention has particular applicability to a crosspoint switching large scale intergration (LSI) for switching data in an asynchronous transfer mode (ATM) in an integrated services digital network (ISDN).
2. Description of the Background Art
Recently, expectation to an asynchronous transfer mode (hereinafter referred to ATM) in a Broadband Integrated Services Digital Network (hereinafter referred to BISDN) has been increasing. An ATM is known as a network applicable to communication services of various transfer rates, and also of various conversion modes.
FIG. 11 is a conceptional view showing a conception of a communication system utilizing an ATM. Referring to FIG. 11, a user terminal 201 is connected to an ATM exchange device 202 in an BISDN network 200 via a subscriber line. In the ATM, a series of data to be transmitted are divided into short data blocks called "ATM cells". Each ATM cell is inserted into a time slot repeated at predetermined cycle, and is transmitted. Each ATM cell includes a header section HD having a destination address, and a data section DT having data to be transmitted. One ATM cell has a data length of 53 bites in total.
Referring to FIG. 12, the ATM exchange device 202 includes input lines 241, 242, . . . and output lines 251, 252, . . . . The input lines 241, 242, . . . are connected to user terminals, for example, via subscriber lines. The output lines 251, 252, . . . are connected to devices to which data are directed. The ATM exchange device 202 receives an ATM cell serially via each input lines 241, 242, . . ., and selectively outputs the same to one of the output lines 251, 252, . . . according to a destination address in the header section HD of the ATM cell. The above exchange operation is carried out for each ATM cell.
FIG. 13 is a block diagram of a conventional ATM exchange device. The ATM exchange device shown in FIG. 13 is described in DIGEST OF TECHNICAL PAPERS, 1990 IEEE International Solid-State Circuits Conference, pp. 30-31. Referring to FIG. 13, packet buffers 231 to 23m respectively receive ATM cells to be transmitted. The ATM cells temporarily held in the packet buffers 231 to 23m are applied to a crosspoint switching LSI (a crosspoint switching device) 220 via the input lines 211 to 21m. A scheduling module 230 receives switching control data for the crosspoint switching LSI 220 from the ATM cells in the packet buffers 231 to 23m, and applies the switching control data SCD to the crosspoint switching LSI 220, referring to destination addresses in the header sections HD of the ATM cells.
The crosspoint switching LSI 220 selectively connects an input line and an output line at each time slot in response to the switching control data SCD, and thus the ATM cells on the input lines 211 to 21m are led to the output lines 221 to 22n in response to the destination addresses included therein.
FIG. 14 is a block diagram of a conventional crosspoint switching LSI. Referring to FIG. 14, a crosspoint switching LSI 300 includes a switch cell matrix 106 in which unit switch cells 105 are arranged in m rows and n columns, an input data register 101 connected to the input lines 211 to 21m, an output data register 102 connected to the output lines 221 to 22n, a switching control register 104 holding switching control data, and a row selecting decoder 103.
One unit switch cell 105 includes a master latch circuit 111, a slave latch circuit 110, and a tristate buffer 109. The master latch circuit 110 holds a switching control signal CNT at a present time slot, while the slave latch circuit 111 holds a switching control signal at a subsequent time slot. The tristate buffer 109 electrically connects an input data line 107 and an output data line 108 in response to the present switching control signal CNT latched in the master latch circuit 110.
FIG. 15 is a circuit block diagram of the switch cell matrix 106 shown in FIG. 14. Referring to FIG. 15, switch cells are arranged in m rows and n columns. For example, the one switch cell 105 is connected to the input data line 107 and the output data line 108. The m input data lines are arranged in a row direction, and connected respectively to the corresponding input latch circuits in the input data register 101. The n output data lines are arranged in a column direction, and connected respectively to the corresponding output latch circuits in the output data line register 102.
FIG. 16 is a schematic diagram a circuit of a conventional unit switch cell. Referring to FIG. 16, the switch cell includes the tristate buffer 109, the slave latch circuit 110, and the master latch circuit 111. The tristate buffer 109 includes NMOS transistors 120 and 121 serially connected between a power supply potential V.sub.DD and a ground potential V.sub.SS and two NOR gates 122 and 123.
The tristate buffer 109 operates as follows. First, when the slave latch circuit 110 holds the switch control signal CNT at a low level, the tristate buffer 109 electrically connects the input data line 107 and the output data line 108. More specifically, when the input data line 107 is at a high level, the output data line 108 is at a low level. When the input data line 107 is at a low level, the output data line 108 is at a high level. In other words, data on the input data line 107 is transmitted to the output data line 108.
When the slave latch circuit 110 holds the switching control signal CNT at a high level, the input data line 107 and the output data line 108 are not electrically connected. More specifically, since both of the transistors 120 and 121 are turned off, the output data line 108 is rendered in a high impedance state with respect to an output of the tristate buffer 109. Data on the input data line 107 is not transmitted to the output data line 108.
The switching control signal CNT for controlling the tristate buffer 109 is applied as follows. Referring to FIG. 17, it is assumed that four ATM cells AC1 to AC4 in time slots TS1 to TS4 are applied to the input lines 241, 242, . . . of the AMT exchange device 202 shown in FIG. 12. The switching control register 104 (shown in FIG. 14) temporarily holds a switching control signal in response to a destination address included in the header section HD of each ATM cell.
In the time slot TS1, as shown in FIG. 17, it is assumed that the slave latch circuit 110 latches a switching control signal CNT 1, and that the master latch circuit 111 holds a switching control signal CNT 2. The slave latch circuit 110 provides the present switching control signal CNT 1 as an output, so that the tristate buffer 109 connects the input data line 107 and the output data line 108 in response to the signal CNT 1. The ATM cell AC1 on the input data line 107 is then applied to the output data line 108.
In the subsequent time slot TS2, being provided with an update signal UD via a signal line 114, the slave latch circuit 110 holds the switching control signal CNT 2 held in the master latch circuit 111. The master latch circuit 111 holds a new switching control signal CNT 3 on a signal line 113 in response to a selecting signal SEL applied from a row selecting decoder (shown in FIG. 14). In response to the switching control signal CNT 2 held in the slave latch circuit 110, the tristate buffer 109 connects the input data line 107 and the output data line 108 in the time slot TS2, so that the ATM cell AC2 on the input data line 107 is applied to the output data line 108.
By repeating the above operation for each time slot, ATM cells on the input data line are applied to the output data line. Although in the above description, the ATM cells AC1 and AC2 are transmitted between the same input data line 107 and the same output data line 108 in the two time slots TS1 and TS2, if the destination address in the ATM cell AC2 is different from that in the ATM cell AC1, the tristate buffer 109 shown in FIG. 16 is turned off, and a tristate buffer in another row is turned on. As a result, an ATM cell on an input data line of another row is applied to the output data line 108.
When the unit switch cell shown in FIG. 16 is used in a crosspoint LSI, the following problems arise. First, a slow operation rate of the tristate buffer 109 is pointed out. An output voltage for driving the output data line 108 is output in response to gate voltages VG1 and VG2 of the transistors 120 and 121. The output data line 108 could not be driven at a high speed, since the input data line 107 has its level changed within a range of a MOS level, 0 to 5 volts.
In addition, four MOS transistors are generally required for constitution of one NOR gate, and thus, the tristate buffer 109 shown in FIG. 16 requires ten MOS transistors in total. This increases an occupied area of the crosspoint switching LSI on a semiconductor substrate. More specifically, integration of the crosspoint switching LSI has been reduced and the number of lines which can be switched has been restricted.